
ADP5586 Data Sheet
Rev. 0 | Page 38 of 44
LOGIC_FF_CFG, Register 0x37
Table 64. LOGIC_FF_CFG Bit Descriptions
Bits Bit Name Access Description
[7:2] Reserved Reserved Reserved.
1 FF_SET Read/write 0 = FF not set in the logic block. Refer to Figure 19.
1 = sets FF in the logic block.
0 FF_CLR Read/write 0 = FF not cleared in the logic block. Refer to Figure 19.
1 = clears FF in the logic block.
LOGIC_INT_EVENT_EN, Register 0x38
Table 65. LOGIC_INT_EVENT_EN Bit Descriptions
Bits Bit Name Access Description
2 LY_DBNC_DIS Read/write 0 = output of the logic block is debounced before entering the event/interrupt block.
1 = output of the logic block is not debounced before entering the event/interrupt block.
Use with caution because glitches may generate interrupts prematurely.
1 LOGIC_EVENT_EN Read/write 0 = LY cannot generate interrupt.
1 = allows LY activity to generate events on the FIFO.
0 LOGIC_INT_LEVEL Read/write Configures the logic level of LY that generates an interrupt.
0 = LY is active low.
1 = LY is active high.
POLL_TIME_CFG, Register 0x39
Table 66. POLL_TIME_CFG Bit Descriptions
Bits Bit Name Access Description
[7:4] Reserved Reserved Reserved.
3 PRECHARGE_TIME Read/write Defines time to allow precharge.
0 = 100 µs.
1 = 200 µs.
2 Reserved Reserved Reserved.
[1:0] KEY_POLL_TIME[1:0] Read/write Configures time between consecutive scan cycles.
00 = 10 ms.
01 = 20 ms.
10 = 30 ms.
11 = 40 ms.
PIN_CONFIG_A, Register 0x3A
Table 67. PIN_CONFIG_A Bit Descriptions
Bits Bit Name Access Description
[7:6] Reserved Reserved Reserved.
5 R5_CONFIG Read/write 0 = GPIO 6.
1 = Row 5.
4 R4_CONFIG Read/write 0 = GPIO 5 (see R4_EXTEND_CFG in Table 69 for alternate configuration, RESET).
1 = Row 4
3 R3_CONFIG Read/write 0 = GPIO 4 (see R3_EXTEND_CFG in Table 69 for alternate configuration, LC).
1 = Row 3
2 R2_CONFIG Read/write 0 = GPIO 3
1 = Row 2
1 R1_CONFIG Read/write 0 = GPIO 2
1 = Row 1
0 R0_CONFIG Read/write 0 = GPIO 1/LY (see R0_EXTEND_CFG in Table 69 for alternate configuration, LY).
1 = Row 0
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